Martin Roth cc827d9aab soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off ... When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=b:277997811 TEST=Build Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74527 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2023-04-21 15:33:09 +00:00
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amd	soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off	2023-04-21 15:33:09 +00:00
cavium	treewide: Remove duplicated include <device/pci.h>	2023-02-01 03:03:34 +00:00
example/min86
intel	soc/intel/meteorlake: Add VPU into the DMAR SATC table	2023-04-21 15:23:49 +00:00
mediatek	soc/mediatek: Add assert for regulator VRF12	2023-04-14 12:09:24 +00:00
nvidia	treewide: stop calling custom TPM log "TCPA"	2023-01-11 16:00:55 +00:00
qualcomm	qualcomm/common: Pass FMAX_LIMIT flag for Lazor board to QcLib	2023-03-17 00:34:08 +00:00
rockchip
samsung	treewide: Fix old-style declarations	2023-01-17 04:23:49 +00:00
sifive/fu540
ti
ucb/riscv