coreboot/src
Florian Zumbiehl fa48b96908 k8 raminit: fix bug, improve clock selection, add clock limit for sock754
in amdk8 raminit:
- fix DDR SPD offset for (CLX - 1) (25 instead of 26)
- improve clock/CL selection algorithm
- implement load-dependent clock limiting for socket 754

Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/377
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-23 01:05:40 +01:00
..
arch/x86 Fix post_code in 16bit entry 2011-11-22 11:17:07 +01:00
boot selfboot: Don't include unneeded ip_checksum.h 2011-11-08 21:21:55 +01:00
console remove trailing whitespace 2011-11-01 19:07:45 +01:00
cpu k8 raminit: add workaround for erratum #181 on non-fam-f 2011-11-22 22:20:30 +01:00
devices remove trailing whitespace 2011-11-01 19:07:45 +01:00
drivers remove trailing whitespace 2011-11-01 19:07:45 +01:00
ec Lenovo H8: Fix h8_set_audio_mute() 2011-10-25 17:48:41 +02:00
include remove trailing whitespace 2011-11-01 19:07:45 +01:00
lib don't scan beyond end of CBFS 2011-11-02 10:49:24 +01:00
mainboard mainboard: Add AMD unionstation RDK support 2011-11-18 21:44:02 +01:00
northbridge k8 raminit: fix bug, improve clock selection, add clock limit for sock754 2011-11-23 01:05:40 +01:00
pc80 Fix checksum calculation both in romstage and ramstage. 2011-10-28 09:09:40 +02:00
southbridge compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD 2011-11-10 23:55:11 +01:00
superio implement hwmon fan divisor setting for w83697hf 2011-11-22 23:07:03 +01:00
vendorcode Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6 2011-10-14 22:57:11 +02:00
Kconfig refactor vesa mode setting code and bootsplash code 2011-10-13 20:00:50 +02:00
Kconfig.deprecated_options some ifdef --> if fixes 2011-04-21 20:24:43 +00:00