coreboot/src/northbridge/intel
Arthur Heymans f8daf86282 nb/intel/sandybridge/acpi: Support setting PCI bars above 4G
Although coreboot can allocate resources above 4G, Linux does not
consider those allocation valid when there is no region above 4G in
_CRS and disables the device.

TESTED: x220 with and external GPU via the expresscard slot. Linux
does not touch the BARs allocated above 4G.

Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-03-28 15:28:19 +00:00
..
common nb/intel/common: Replace _bar_clrsetbits_impl macro 2021-05-03 07:38:52 +00:00
e7505 timestamps: Rename timestamps to make names more consistent 2022-03-08 16:06:33 +00:00
gm45 nb/intel/gm45/pm.c: Make clang happy 2022-03-25 19:59:20 +00:00
haswell timestamps: Rename timestamps to make names more consistent 2022-03-08 16:06:33 +00:00
i440bx timestamps: Rename timestamps to make names more consistent 2022-03-08 16:06:33 +00:00
i945 timestamps: Rename timestamps to make names more consistent 2022-03-08 16:06:33 +00:00
ironlake timestamps: Rename timestamps to make names more consistent 2022-03-08 16:06:33 +00:00
pineview timestamps: Rename timestamps to make names more consistent 2022-03-08 16:06:33 +00:00
sandybridge nb/intel/sandybridge/acpi: Support setting PCI bars above 4G 2022-03-28 15:28:19 +00:00
x4x timestamps: Rename timestamps to make names more consistent 2022-03-08 16:06:33 +00:00