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coreboot/src/soc/intel
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Andrey Petrov f748f83ecb soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage 
Use postcar infrastructure to enable caching of area where ramstage
runs.

Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14095
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:16:02 +02:00
..
apollolake soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage 2016-04-28 05:16:02 +02:00
baytrail soc/intel: Update license headers 2016-04-14 16:54:33 +02:00
braswell soc/intel: Update license headers 2016-04-14 16:54:33 +02:00
broadwell soc/intel: Update license headers 2016-04-14 16:54:33 +02:00
common src/soc/intel/common: Fix CID 1295499, remove dead code 2016-04-13 07:00:27 +02:00
fsp_baytrail intel/fsp_baytrail: Eliminate warning about missing set_resources 2016-04-16 02:04:41 +02:00
fsp_broadwell_de intel/fsp_broadwell_de: fix SPD CBFS file type 2016-04-20 23:37:29 +02:00
quark soc/intel/quark: Fix MTRR reads 2016-04-22 17:45:03 +02:00
skylake soc/intel: Update license headers 2016-04-14 16:54:33 +02:00