Felix Held 556d1cc17f soc/amd/*/i2c: factor out common I2C pad configuration ... The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2022-02-03 23:46:00 +00:00
..
acpi	soc/amd/cezanne/acpi: Add support for RTC workaround	2021-12-18 12:23:21 +00:00
include/soc	soc/amd/*/i2c: factor out common I2C pad configuration	2022-02-03 23:46:00 +00:00
psp_verstage	soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode	2022-02-02 22:56:43 +00:00
acpi.c	soc/amd/cezanne,picasso,sabrina: factor out get_threads_per_core	2022-01-26 04:15:11 +00:00
agesa_acpi.c	soc/amd/cezanne: Generate IVRS for cezanne	2021-08-05 15:54:50 +00:00
aoac.c	soc/amd/cezanne: factor out AOAC offset defines	2021-06-16 16:38:25 +00:00
bootblock.c	soc/amd/cezanne,picasso: factor out common early non-car cache setup	2022-01-20 22:28:50 +00:00
chip.c	soc/amd/cezanne/chip: add functionality to power down eMMC interface	2021-08-29 20:58:51 +00:00
chip.h	soc/amd/*/i2c: factor out common I2C pad configuration	2022-02-03 23:46:00 +00:00
chipset.cb	soc/amd/cezanne,picasso/chipset.cb: drop LAPIC device	2021-10-22 14:59:24 +00:00
config.c	src: Add missing 'void' in function definition	2022-01-26 23:57:12 +00:00
cppc.c	acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table	2021-10-21 20:03:14 +00:00
cpu.c	soc/amd/*/cpu: handle mp_init_with_smm failure	2021-11-03 18:37:28 +00:00
data_fabric.c	soc/amd/*/data_fabric: use DF_ prefix for bit and shift defines	2021-11-25 18:46:16 +00:00
early_fch.c	src/soc/amd: Remove unused <console/console.h>	2022-01-10 18:40:56 +00:00
espi_util.c	soc/amd/cezanne: factor out eSPI SPI2 pads configuration functions	2022-01-14 00:29:52 +00:00
fch.c	soc/amd/cezanne/fch: disable 48MHz output in S0i3	2021-12-20 17:39:29 +00:00
fsp_m_params.c	soc/amd/cezanne: FSP: Add UPD entry for eDP tuning	2022-01-25 23:57:06 +00:00
fsp_s_params.c	soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE	2021-07-19 14:58:53 +00:00
fw.cfg	soc/amd/cezanne: Add PSP whitelist debug unlock support	2021-03-01 08:27:57 +00:00
gpio.c	soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h	2021-09-23 18:33:00 +00:00
graphics.c	soc/amd/cezanne/graphics: add VBIOS ID remapping for Barcelo	2021-07-17 21:32:59 +00:00
i2c.c	soc/amd/*/i2c: factor out common I2C pad configuration	2022-02-03 23:46:00 +00:00
Kconfig	soc/amd/*/i2c: factor out common I2C pad configuration	2022-02-03 23:46:00 +00:00
Makefile.inc	soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI	2022-02-02 23:31:51 +00:00
mca.c	soc/amd/cezanne/mca: add and use mca_bank_name[]	2021-07-21 22:38:11 +00:00
preload.c	soc/amd/cezanne: Preload FSP-S	2021-11-12 14:55:45 +00:00
reset.c	soc/amd/cezanne: remove warm reset flag code	2021-06-11 21:48:28 +00:00
romstage.c	soc/amd/cezanne: Move APOB update into ramstage	2021-07-14 17:54:36 +00:00
root_complex.c	soc/amd: factor out acpigen_write_alib_dptc to common code	2021-05-13 00:58:26 +00:00
smihandler.c	soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPI	2021-12-08 17:52:03 +00:00
smu.c	soc/amd/cezanne: add SMU support	2021-03-04 19:55:27 +00:00
uart.c	soc/amd/cezanne,picasso/uart: implement read_resource	2021-10-15 14:46:58 +00:00
xhci.c	soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h	2021-09-23 18:33:00 +00:00