Sean Rhodes f71d8c94ea soc/tigerlake: Make IO decode / enable register configurable ... This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>		2021-10-01 18:53:28 +00:00
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amd	soc/amd/cezanne/early_fch: move mb_set_up_early_espi into if block	2021-09-27 13:40:34 +00:00
cavium
example	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
intel	soc/tigerlake: Make IO decode / enable register configurable	2021-10-01 18:53:28 +00:00
mediatek	soc/mediatek/mt8195: initialize DFD	2021-09-29 06:57:15 +00:00
nvidia	drivers/gic: Remove unnecessary code	2021-10-01 00:01:56 +00:00
qualcomm	soc/qualcomm/sc7280: Enable QUP drivers to use lz4 compression	2021-09-27 21:35:31 +00:00
rockchip	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive	memlayout: Store region sizes as separate symbols	2021-02-19 08:39:26 +00:00
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb