coreboot/src/soc
Subrata Banik 6876f49b7e soc/intel/meteorlake: Refactor bootblock SoC programming code
This patch ensures the IP initialization being done as part of MTL
bootblock code is able to complete the bootblock phase without any
visible hang.

The re-ordering in the MTL bootblock SoC programming is required to
ensure the SA early initialization is taking place prior to
performing any PCI Read/Write operation (like P2SB bar enabling for
IOE die etc.).

Additionally, Fast SPI init takes place prior to enabling ROM caching
etc.

BUG=b:224325352
TEST= Able to build and start booting the MTL simics.
Without this change, the code execution is stuck as below:

[NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz
[DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG]  IGD: device id ffff (rev ff) is Unknown
[INFO ]  PMC: Using default GPE route.
[INFO ]  VBNV: CMOS invalid, restoring from flash
[ERROR]  init_vbnv: failed to locate NVRAM
[EMERG]  Cannot locate primary CBFS

Able to detect the Flash and reading the SPI flash layout in proper
with this change as below:
[NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz
[DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG]  IGD: device id ffff (rev ff) is Unknown
[INFO ]  PMC: Using default GPE route.
[INFO ]  VBNV: CMOS invalid, restoring from flash
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1804000.
[DEBUG]  FMAP: base = 0x0 size = 0x2000000 #areas = 33
[DEBUG]  FMAP: area RW_NVRAM found @ 112b000 (24576 bytes)
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-06 17:52:32 +00:00
..
amd amdblocks/smm.h: Add header guards 2022-06-03 15:22:28 +00:00
cavium i2c: Add configurable I2C transfer timeout 2022-03-15 22:06:27 +00:00
example
intel soc/intel/meteorlake: Refactor bootblock SoC programming code 2022-06-06 17:52:32 +00:00
mediatek soc/mediatek: Rename mtk_wdt_preinit() to mtk_wdt_set_req() 2022-06-03 15:27:26 +00:00
nvidia soc/*: Use __fallthrough statement 2022-05-11 06:04:25 +00:00
qualcomm sc7180: Trogdor to support 2 dcb 2022-06-01 18:05:38 +00:00
rockchip soc/*: Use __fallthrough statement 2022-05-11 06:04:25 +00:00
samsung i2c: Add configurable I2C transfer timeout 2022-03-15 22:06:27 +00:00
sifive
ti treewide: Remove "ERROR: "/"WARN: " prefixes from log messages 2022-02-07 23:29:09 +00:00
ucb