Elyes HAOUAS 985821c4f2 cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE ... Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE". It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets should have at least 256K L2 cache. That is plenty for XIP RO cache of bootblock + romstage and a 32K CAR. Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2021-01-21 09:08:14 +00:00
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amd	kconfig: remove non-existent source	2020-12-28 13:37:56 +00:00
intel	cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE	2021-01-21 09:08:14 +00:00