Jeremy Compostella e68650a656 vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header file ... Export Power State Current 1, 2 and 3 Threshold configuration entries. BUG=b:308002192 Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e6 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>		2023-10-28 20:57:52 +00:00
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edk2	vendorcode/intel/edk2: Use C99 flexible arrays	2023-08-26 21:17:24 +00:00
fsp	vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header file	2023-10-28 20:57:52 +00:00
Kconfig	vc/intel: Remove unnecessary Kconfig options	2023-08-26 21:14:45 +00:00
Makefile.inc	vc/intel/edk2: Remove edk2-stable202111 support	2023-06-17 09:20:52 +00:00