Felix Held f6421311c9 soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro ... Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75596 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>		2023-06-07 00:29:39 +00:00
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amd	soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro	2023-06-07 00:29:39 +00:00
cavium	soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register	2023-05-13 17:22:16 +00:00
example/min86
intel	soc/intel/common/crashlog: Add support for IOE die	2023-06-06 17:34:53 +00:00
mediatek	mb/google/geralt: Fix MIPI panel power on/off sequence	2023-06-06 12:16:26 +00:00
nvidia
qualcomm	treewide: Remove 'extern' from functions declaration	2023-05-26 13:45:24 +00:00
rockchip
samsung
sifive/fu540	soc/sifive: Comment out set but unused variables	2023-06-04 19:22:50 +00:00
ti
ucb/riscv