coreboot/src/soc/intel
Furquan Shaikh f5b30eda1f commonlib/region: Allow multiple windows for xlate_region_dev
This change updates the translated region device (xlate_region_dev) to
support multiple translation windows from the 1st address space to
2nd address space. The address spaces described by the translation
windows can be non-contiguous in both spaces. This is required so that
newer x86 platforms can describe memory mapping of SPI flash into
multiple decode windows in order to support greater than 16MiB of
memory mapped space.

Since the windows can be non-contiguous, it introduces new
restrictions on the region device ops - any operation performed on the
translated region device is limited to only 1 window at a time. This
restriction is primarily because of the mmap operation. The caller
expects that the memory mapped space is contiguous, however, that is
not true anymore. Thus, even though the other operations (readat,
writeat, eraseat) can be updated to translate into multiple operations
one for each access device, all operations across multiple windows are
prohibited for the sake of consistency.

It is the responsibility of the platform to ensure that any section
that is operated on using the translated region device does not span
multiple windows in the fmap description.

One additional difference in behavior is xlate_region_device does not
perform any action in munmap call. This is because it does not keep
track of the access device that was used to service the mmap
request. Currently, xlate_region_device is used only by memory mapped
boot media on the backend. So, not doing unmap is fine. If this needs
to be changed in the future, xlate_region_device will have to accept a
pre-allocated space from the caller to keep track of all mapping
requests.

BUG=b:171534504

Change-Id: Id5b21ffca2c8d6a9dfc37a878429aed4a8301651
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47658
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 18:59:18 +00:00
..
alderlake soc/intel/alderlake: Align chipset.cb with pci_devs.h 2020-12-04 21:10:19 +00:00
apollolake commonlib/region: Allow multiple windows for xlate_region_dev 2020-12-08 18:59:18 +00:00
baytrail src: Remove redundant use of ACPI offset(0) 2020-12-03 00:05:52 +00:00
braswell cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
broadwell src: Remove redundant use of ACPI offset(0) 2020-12-03 00:05:52 +00:00
cannonlake soc/intel/{skl,cnl}: add NMI_{EN,STS} registers 2020-12-04 00:10:38 +00:00
common soc/intel/common/gpio_defs: Add PAD_TRIG(OFF) in PAD_CFG_GPI_GPIO_DRIVER 2020-12-08 16:56:00 +00:00
denverton_ns src: Remove redundant use of ACPI offset(0) 2020-12-03 00:05:52 +00:00
elkhartlake soc/intel/elkhartlake: Update Kconfig 2020-12-02 10:44:48 +00:00
icelake soc/intel: Configure P2SB before other PCH controllers 2020-11-29 17:18:02 +00:00
jasperlake soc/intel/jasperlake: Add Acoustic noise mitigation configuration 2020-12-05 08:11:16 +00:00
quark cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() 2020-12-03 00:00:19 +00:00
skylake soc/intel/skl: set PEG port state to auto 2020-12-07 14:07:17 +00:00
tigerlake soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devices 2020-11-30 08:06:13 +00:00
xeon_sp soc/intel/xeon_sp: Don't use common block acpi.h 2020-12-05 08:10:33 +00:00
Kconfig