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coreboot/src/mainboard/google/fizz
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Aaron Durbin 33c3dd80e8 UPSTREAM: lib/spd_bin: make SMBus SPD addresses an input 
Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.

BUG=none
BRANCH=none
TEST=none

Change-Id: I1ef87d18b30192be730805238df62ff81f130339
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dd82edc388
Original-Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19915
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/517936
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-05-29 01:59:18 -07:00
..
acpi
acpi_tables.c
board_info.txt
boardid.c
bootblock.c
chromeos.c UPSTREAM: mb/google/fizz: Set lid status as open 2017-04-26 09:20:59 -07:00
chromeos.fmd
devicetree.cb UPSTREAM: google/fizz: Enable devices under pci 1c.0 2017-05-07 16:25:49 -07:00
dsdt.asl
ec.c
ec.h
gpio.h UPSTREAM: google/fizz: Set GPP_C2 to NC 2017-05-29 01:59:18 -07:00
Kconfig UPSTREAM: google/fizz: Configure memory 2017-04-26 09:20:55 -07:00
Kconfig.name
mainboard.c
Makefile.inc
ramstage.c
romstage.c UPSTREAM: lib/spd_bin: make SMBus SPD addresses an input 2017-05-29 01:59:18 -07:00
smihandler.c