f4e6466924
Add the pin definitions for the remote GPIOs and the GPIO pin mux values for the GPIO mode of those pins. For now, accessing the remote GPIOs is only supported from the native coreboot code running on the x86 cores and not from verstage on PSP or ACPI. BUG=b:194524995 TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and then toggling that GPIO in an infinite loop in the mainboard's bootblock code results in GPIO 262 toggling as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> |
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| .. | ||
| cezanne | ||
| common | ||
| picasso | ||
| stoneyridge | ||
| Kconfig | ||