coreboot/src/southbridge
Dave Frodin f364fc7682 southbridge/amd/pi: Enable early I/O decode to LPC
The decode of UART addresses down to the LPC bus needs
to occur early to allow romstage console messages to
be seen. This enables the decode of most of the I/O
ports typically seen in a system.

Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-17 17:49:58 +01:00
..
amd southbridge/amd/pi: Enable early I/O decode to LPC 2015-03-17 17:49:58 +01:00
broadcom x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer 2015-02-15 08:50:22 +01:00
dmp southbridge/dmp/vortex86ex/southbridge.c: Silence bitwise op warns 2014-12-07 21:11:58 +01:00
intel Intel common SPI: Fix compilation breakage from refactoring 2015-03-17 04:55:52 +01:00
nvidia nvidia/ck804: Minor cleanup on dead code 2015-02-16 23:14:18 +01:00
rdc southbridge: Trivial - drop trailing blank lines at EOF 2014-07-08 13:53:21 +02:00
ricoh southbridge/ricoh: Spelling fixes 2014-12-17 16:54:03 +01:00
sis x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer 2015-02-15 08:50:22 +01:00
ti southbridge/ricoh,ti: Remove trailing whitespace in debug output 2014-08-10 08:27:41 +02:00
via x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer 2015-02-15 08:50:22 +01:00
Kconfig Add support for DMP Vortex86EX PCI southbridge. 2013-07-03 18:31:22 +02:00
Makefile.inc Add support for DMP Vortex86EX PCI southbridge. 2013-07-03 18:31:22 +02:00