coreboot/src/cpu/intel
Tim Wawrzynczak f2cae5085c cpu/intel/car: Add EC software sync to Intel romstage
Perform EC software sync in romstage, before memory training is started.
Because the ChromeOS EC will not currently perform USB-PD negotiation
until it jumps to running its RW code, this allows the system to get
access to more power earlier in the boot flow.

This is guarded by CONFIG_VBOOT_EARLY_EC_SYNC.

BUG=b:112198832
BRANCH=none
TEST=EC software sync works in update and non-update case.
No significant effect on boot time (~6 ms).

Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36211
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20 13:31:13 +00:00
..
car cpu/intel/car: Add EC software sync to Intel romstage 2019-11-20 13:31:13 +00:00
common Rangeley: Fix incorrect BCLK 2019-11-07 14:08:46 +00:00
fit security/intel: Add TXT infrastructure 2019-09-02 04:52:04 +00:00
fsp_model_406dx arch/x86: Drop some __SMM__ guards 2019-11-08 07:46:23 +00:00
haswell cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
hyperthreading cpu/intel/common: Move intel_ht_sibling() to common folder 2019-10-01 15:10:16 +00:00
microcode console: Declare empty printk() for __ROMCC__ 2019-09-30 08:40:58 +00:00
model_6bx AUTHORS: Move src/cpu/intel copyrights into AUTHORS file 2019-09-10 12:51:10 +00:00
model_6ex cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
model_6fx cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
model_6xx Use 3rdparty/intel-microcode 2019-07-01 10:26:12 +00:00
model_65x AUTHORS: Move src/cpu/intel copyrights into AUTHORS file 2019-09-10 12:51:10 +00:00
model_67x AUTHORS: Move src/cpu/intel copyrights into AUTHORS file 2019-09-10 12:51:10 +00:00
model_68x AUTHORS: Move src/cpu/intel copyrights into AUTHORS file 2019-09-10 12:51:10 +00:00
model_106cx cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
model_206ax nb/intel/sandybridge: Set up console in bootblock 2019-11-18 11:48:35 +00:00
model_1067x cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
model_2065x arch/x86: Drop some __SMM__ guards 2019-11-08 07:46:23 +00:00
model_f2x cpu/intel/common: Move intel_ht_sibling() to common folder 2019-10-01 15:10:16 +00:00
model_f3x cpu/intel/common: Move intel_ht_sibling() to common folder 2019-10-01 15:10:16 +00:00
model_f4x cpu/intel: Drop SMM_TSEG conditional 2019-07-09 12:45:48 +00:00
slot_1 intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER 2019-11-05 14:38:17 +00:00
smm/gen1 cpu/intel/smm/gen1: Deal with SMM save state compatibility 2019-11-04 11:37:42 +00:00
socket_441 nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK 2019-11-15 16:45:48 +00:00
socket_BGA956 nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support 2019-10-28 11:59:17 +00:00
socket_FCBGA559
socket_LGA775 nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK 2019-11-15 18:06:27 +00:00
socket_m nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK 2019-11-15 16:45:48 +00:00
socket_mPGA604 cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE 2019-11-03 06:15:35 +00:00
socket_p nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support 2019-10-28 11:59:17 +00:00
speedstep AUTHORS: Move src/cpu/intel copyrights into AUTHORS file 2019-09-10 12:51:10 +00:00
thermal_monitoring
turbo AUTHORS: Move src/cpu/intel copyrights into AUTHORS file 2019-09-10 12:51:10 +00:00
Kconfig
Makefile.inc cpu/intel/common: Move intel_ht_sibling() to common folder 2019-10-01 15:10:16 +00:00