coreboot/southbridge
Mart Raudsepp d7048f10ca cs5536: Fix NAND Flash setup.
A NAND device may never be mapped above 0xEFFFFFFF, as these addresses never reach
the NAND controller. Only NAND controller, as the only DIVIL component that is
allowed to be memory mapped, is affected - other Geode LX and CS5536 peripherals
(that are separate GLIU devices outside DIVIL component) can use addresses above
that limit (see in-code comment for details).

In combination with a new VSA2 version 1.02 or newer, this makes NAND flash
finally work in coreboot v3.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1125 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-09 16:10:58 +00:00
..
amd cs5536: Fix NAND Flash setup. 2009-02-09 16:10:58 +00:00
intel Port r3747, r3732, r3733 from v2 to v3 (build-tested on v3): 2009-01-08 16:14:12 +00:00
nvidia This trivial patch adds the warnings Peter and Ron requested to the ck804 code. 2009-01-07 18:37:21 +00:00
via/vt8237 This patch fixes a few small problems and gets cn700 to read from an IDE 2008-12-23 23:44:39 +00:00