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coreboot/src/cpu/intel
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Alexander Couzens f251a6d7d4 cpu/intel: >= nehalem: add comments to msr finalize's 
Improve documentation of lock down MSRs in finalize().
Most of these aren't documented in public MSRs.

Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8294
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-11 02:58:06 +01:00
..
car x86 romstage: Move stack just below RAMTOP 2014-10-19 06:14:05 +02:00
ep80579 vboot2: add verstage 2015-01-27 01:41:40 +01:00
fit
fsp_model_206ax cpu/intel: >= nehalem: add comments to msr finalize's 2015-02-11 02:58:06 +01:00
fsp_model_406dx FSP & CBMEM: Fix broken cbmem CAR transition. 2015-02-06 00:53:13 +01:00
haswell cpu/intel: >= nehalem: add comments to msr finalize's 2015-02-11 02:58:06 +01:00
hyperthreading {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs 2014-10-27 23:40:05 +01:00
microcode
model_6bx vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_6dx vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_6ex vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_6fx vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_6xx vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_65x vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_67x vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_68x vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_69x vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_106cx vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_206ax cpu/intel: >= nehalem: add comments to msr finalize's 2015-02-11 02:58:06 +01:00
model_1067x vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_2065x cpu/intel: >= nehalem: add comments to msr finalize's 2015-02-11 02:58:06 +01:00
model_f0x vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_f1x vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_f2x vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_f3x vboot2: add verstage 2015-01-27 01:41:40 +01:00
model_f4x vboot2: add verstage 2015-01-27 01:41:40 +01:00
slot_1 intel CAR: Fix DCACHE_RAM_BASE for old sockets 2014-12-30 10:21:43 +01:00
slot_2 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_441 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_BGA956 Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
socket_FC_PGA370 intel CAR: Fix DCACHE_RAM_BASE for old sockets 2014-12-30 10:21:43 +01:00
socket_LGA771
socket_LGA775
socket_LGA1155 cpu/intel: Add configuration for socket LGA1155 2014-10-29 21:11:11 +01:00
socket_mFCBGA479 intel CAR: Fix DCACHE_RAM_BASE for old sockets 2014-12-30 10:21:43 +01:00
socket_mFCPGA478 Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
socket_mPGA478 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_mPGA479M intel CAR: Fix DCACHE_RAM_BASE for old sockets 2014-12-30 10:21:43 +01:00
socket_mPGA603 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_mPGA604 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_PGA370 intel CAR: Fix DCACHE_RAM_BASE for old sockets 2014-12-30 10:21:43 +01:00
socket_rPGA988B Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
socket_rPGA989 Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
speedstep ibexpeak, bd82x6x: Move to implicit length patching 2014-11-09 02:01:21 +01:00
thermal_monitoring
turbo
Kconfig cpu/intel: Add configuration for socket LGA1155 2014-10-29 21:11:11 +01:00
Makefile.inc cpu/intel: Add configuration for socket LGA1155 2014-10-29 21:11:11 +01:00