Tao Xia f20151dfaa mb/google/dedede/var/storo: Generate SPD ID for supported memory parts ... Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: MT53E512M32D2NP-046 WT:E H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A H9HCNNNCPMMLXR-NEE BUG=None TEST=Build the storo board. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ifd935865927bb9fccf95eb4924ca6986d0c19442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>		2020-12-21 02:37:39 +00:00
..
acpi
arch	arch/arm: Replace .id section with build_info in CBFS	2020-12-17 06:25:25 +00:00
commonlib	coreboot tables: Add SPI flash memory map windows to coreboot tables	2020-12-08 22:56:09 +00:00
console
cpu	arch/x86: Link gdt_init.S into bootblock	2020-12-16 06:31:55 +00:00
device	azalia: Use azalia_enter_reset function	2020-12-17 20:25:09 +00:00
drivers	drivers/intel/fsp2_0: recreate FSP targets on config change	2020-12-21 02:32:16 +00:00
ec
include	device/azalia_device.c: Add codec reset helpers	2020-12-17 13:55:10 +00:00
lib	arch/arm: Replace .id section with build_info in CBFS	2020-12-17 06:25:25 +00:00
mainboard	mb/google/dedede/var/storo: Generate SPD ID for supported memory parts	2020-12-21 02:37:39 +00:00
northbridge	drivers: Replace set_vbe_mode_info_valid	2020-12-17 06:21:56 +00:00
security
soc	soc/intel/xeon_sp/skx: Properly set up MTRR's	2020-12-21 02:37:13 +00:00
southbridge	azalia: Use azalia_enter_reset function	2020-12-17 20:25:09 +00:00
superio
vendorcode	soc/amd/picasso: Add UPDs for support eDP phy tunning adjust	2020-12-21 02:34:32 +00:00
Kconfig	Kconfig: Show console debug options if loglevel override is set	2020-12-11 15:58:24 +00:00