coreboot/src/drivers/intel
Lee Leahy f169a13839 UPSTREAM: drivers/intel/fsp2_0: Update the debug levels
Choose appropriate debug levels for the various messages in the FSP
driver.  Change:

* BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows
  builder to disable FSP driver output by selecting
  CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7

* BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the
  payload from successfully booting

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I36f5ba6e2a0e89b7c1127218b982a105039e90a3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16003
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367382
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-10 13:09:34 -07:00
..
fsp1_0 UPSTREAM: Fix some cbmem.h includes 2016-06-20 20:09:48 -07:00
fsp1_1 UPSTREAM: src/drivers: Capitalize CPU, RAM and ACPI 2016-08-04 23:38:02 -07:00
fsp2_0 UPSTREAM: drivers/intel/fsp2_0: Update the debug levels 2016-08-10 13:09:34 -07:00
gma UPSTREAM: Add newlines at the end of all coreboot files 2016-08-05 11:45:17 -07:00
i210 UPSTREAM: intel/i210: Change API for function mainboard_get_mac_address() 2016-07-07 01:09:39 -07:00
wifi UPSTREAM: intel/wifi: Include conditionally in the build 2016-08-04 23:36:51 -07:00