Patrick Georgi f0a97bf75e google/veyron: Fix building with CHROMEOS enabled ... romstage requires some button accessor functions for the Chrome OS boot flow. Change-Id: I3f90d66b103e0610931c183dd5f5679ca6f910f6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10697 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)		2015-06-30 08:17:52 +02:00
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acpi	acpi/sata: add generic sata ssdt port generator	2015-06-07 01:24:47 +02:00
arch	arch/arm64: Avoid race condition when building bl31	2015-06-30 08:11:39 +02:00
console	consoles: remove unused infrastructure	2015-05-26 19:02:54 +02:00
cpu	cpu: x86 port to 64bit	2015-06-20 18:16:54 +02:00
device	ddr3: add missing newline	2015-06-23 01:50:33 +02:00
drivers	Kconfig: Remove unnecessary and incorrect MRC_CACHE symbols	2015-06-27 02:47:39 +02:00
ec	EC: Add new EC host event for FASTBOOT_MODE request	2015-06-30 08:09:41 +02:00
include	arm64: Add support for loading secure os	2015-06-30 08:10:28 +02:00
lib	hardwaremain: Move init_timer() call to before console init	2015-06-30 08:11:16 +02:00
mainboard	google/veyron: Fix building with CHROMEOS enabled	2015-06-30 08:17:52 +02:00
northbridge	intel raminit: check correct registers in channel_test	2015-06-28 22:42:11 +02:00
soc	t210: Set UTMIP_PCOUNT_UPDN_DIV to 0	2015-06-30 08:10:54 +02:00
southbridge	amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0	2015-06-25 04:06:59 +02:00
superio	superio: use common x86 code on x86-64	2015-06-22 07:36:09 +02:00
vendorcode	Add Kconfig flag to specify if there's a lid switch	2015-06-30 08:10:19 +02:00
Kconfig	southbridge/intel: Create common IFD Kconfig and Makefile	2015-06-23 22:48:45 +02:00