coreboot/src/arch/mips
Ionela Voinescu ef4e87b45b arch/mips: simplify cache operations
Cache operations are simplified by removing assembly
implementation and replacing it with simpler C code.

BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; caches are properly
     invalidated;
BRANCH=none

Change-Id: I0f092660549c368e98c208ae0c991fe6f5a428d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf99849e75813cba865b15af9e110687816e61e4
Original-Change-Id: I965e7929718424f92f3556369d36a18ef67aa0d0
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250792
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9820
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21 08:12:51 +02:00
..
include arch/mips: simplify cache operations 2015-04-21 08:12:51 +02:00
ashldi3.c mips: Add mips/ashldi3.c from Linux 2015-03-21 16:56:54 +01:00
boot.c program loading: unify on struct prog 2015-04-03 14:53:11 +02:00
bootblock.S arch/mips: provide proper cache primitives 2015-04-13 20:25:21 +02:00
bootblock_simple.c urara: Identity map DRAM/SRAM 2015-04-21 08:12:13 +02:00
cache.c arch/mips: simplify cache operations 2015-04-21 08:12:51 +02:00
Kconfig Kconfig: Fix incorrect CONFIG_STACK_SIZE values for X86 and ARM64 2015-04-15 00:22:13 +02:00
Makefile.inc mips: Allow memory to be identity mapped in the TLB 2015-04-21 08:12:07 +02:00
mmu.c mips: Allow memory to be identity mapped in the TLB 2015-04-21 08:12:07 +02:00
stages.c arch/mips: provide proper cache primitives 2015-04-13 20:25:21 +02:00
tables.c mips: fix write_table 2015-03-30 20:41:23 +02:00