a7eb390796
FMAP should not contain information about the memory map.
Done with the following command:
"find -name \*.fmd -exec sed -i 's/\(FLASH\).* \(.*\) /\1 \2 /' {} \;"
for AMD:
All addresses that amdfwtool expects as command line parameter have the
ADDR_REL_BIOS (flash address) address_mode setting. One exception is
the *_FW_A_POSITION and *_FW_B_POSITION addresses. But amdfwtool checks
if memory or flash addresses are passed and converts accordingly. So
changing the address from memory -> flash doesn't matter for the
resulting binary.
Since commit 41a162b7a8 ("soc/amd/phoenix/Makefile.inc: Pass APOB_NV
address as offset") and therefore since phoenix SOC, APOB_NV is passed
as flash offset. But before that the memory ABL always assumed a MMIO
address (no matter the address_mode) so we need to add a little quirk
for that.
tested: boot glinda based mainboard and also check that memory training
is still cached successfully in APOB_NV.
Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
20 lines
526 B
Text
20 lines
526 B
Text
# layout for firmware when flash address space matches used address layout
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# +-------------+ <-- 0
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# | unspecified |
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# +-------------+ <-- BIOS_BASE
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# | bootblock |
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# +-------------+ <-- BIOS_BASE + 128K
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# | FMAP |
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# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE
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# | CBFS |
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# +-------------+ <-- ROM_SIZE
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FLASH ##ROM_SIZE## {
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BIOS@##BIOS_BASE## ##BIOS_SIZE## {
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BOOTBLOCK 128K
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FMAP@##FMAP_BASE## ##FMAP_SIZE##
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##CONSOLE_ENTRY##
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##MRC_CACHE_ENTRY##
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COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
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}
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}
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