coreboot/src
Aaron Durbin eef80a946e UPSTREAM: lib/selfboot: don't open code linked list operations
The list insertion operations were open coded at each location.
Add helper functions which provide the semantics needed by
the selfboot code in a single place.

Change-Id: Ic757255e01934b499def839131c257bde9d0cc93
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15601
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360208
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-07-12 22:34:47 -07:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch UPSTREAM: acpi: Change device properties to work as a tree 2016-07-09 01:39:55 -07:00
commonlib UPSTREAM: lib: Add real-time-clock functions 2016-07-07 01:08:44 -07:00
console UPSTREAM: console/post: be explicit about conditional cmos_post_log() compiling 2016-05-26 03:21:57 -07:00
cpu UPSTREAM: intel post-car: Consolidate choose_top_of_stack() 2016-07-11 21:27:25 -07:00
device UPSTREAM: device: i2c: Add support for I2C bus operations 2016-06-10 00:17:46 -07:00
drivers UPSTREAM: intel post-car: Consolidate choose_top_of_stack() 2016-07-11 21:27:25 -07:00
ec google/chromeec: Update EC command header 2016-06-23 15:15:09 -07:00
include UPSTREAM: SPD: Add CAS latency 2 2016-07-12 22:34:24 -07:00
lib UPSTREAM: lib/selfboot: don't open code linked list operations 2016-07-12 22:34:47 -07:00
mainboard UPSTREAM: Documentation: Fix doxygen errors 2016-07-12 22:34:45 -07:00
northbridge UPSTREAM: nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM 2016-07-11 21:27:15 -07:00
soc UPSTREAM: Documentation: Fix doxygen errors 2016-07-12 22:34:45 -07:00
southbridge UPSTREAM: Documentation: Fix doxygen errors 2016-07-12 22:34:45 -07:00
superio UPSTREAM: sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-31 12:07:04 -07:00
vendorcode UPSTREAM: soc/intel/quark: Pass in the memory initialization parameters 2016-07-09 01:40:13 -07:00
Kconfig UPSTREAM: Romstage spinlocks require EARLY_CBMEM_INIT 2016-07-11 21:27:20 -07:00