coreboot/src/cpu/intel/haswell
Alexandru Gagniuc 1d85700503 cpu: microcode: Use microcode stored in binary format
Using a copiler to compile something that's already a binary is pretty
stupid. Now that Stefan converted most microcode in blobs to a plain
binary, use the binary version.

Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11607
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30 06:57:19 +00:00
..
acpi Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
acpi.c device_ops: add device_t argument to acpi_fill_ssdt_generator 2015-06-05 21:11:43 +02:00
bootblock.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
cache_as_ram.inc Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig 2015-08-25 17:36:45 +00:00
chip.h intel: Remove pstate_coord_type. 2015-05-28 11:19:21 +02:00
finalize.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
haswell.h Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
haswell_init.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
Kconfig smm: Merge configs SMM_MODULES and SMM_TSEG 2015-05-28 22:07:58 +02:00
Makefile.inc cpu: microcode: Use microcode stored in binary format 2015-09-30 06:57:19 +00:00
monotonic_timer.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
romstage.c coreboot: move TS_END_ROMSTAGE to one spot 2015-09-24 16:12:44 +00:00
smmrelocate.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
stage_cache.c haswell: Link stage_cache_external_region into ramstage, too 2015-05-05 03:39:41 +02:00
tsc_freq.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00