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Mario Scheithauer ed784bc0a7 mb/siemens/mc_ehl: Disable HECI #2 device 
HECI #2 is not used for CSE communication. Therefore, it is not
necessary to set the parameter 'Heci2Enable' in devicetree.

Change-Id: I7012e4d877a464699727ca775af3f9965e0602e9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-15 11:12:22 +00:00
..
acpi Rename ECAM-specific MMCONF Kconfigs 2021-11-10 17:24:16 +00:00
arch Add ENV_STAGE_SUPPORTS_SMP to clean up spinlock stubs 2021-11-13 22:26:53 +00:00
commonlib drivers/intel/fsp2_0: Allow FSP-M to be relocated 2021-11-08 19:58:46 +00:00
console src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
cpu cpu/intel: Use unsigned types in get_cpu_count() 2021-11-05 15:30:34 +00:00
device device/azalia_device: Drop unused function parameter 2021-11-11 22:45:04 +00:00
drivers drivers/wifi/generic: fix package_size to align with WLAN driver 2021-11-15 09:59:44 +00:00
ec ChromeOS: Fix <vc/google/chromeos/chromeos.h> 2021-11-09 00:14:46 +00:00
include Add ENV_STAGE_SUPPORTS_SMP to clean up spinlock stubs 2021-11-13 22:26:53 +00:00
lib arch/x86: Refactor the SMBIOS type 17 write function 2021-11-11 09:10:10 +00:00
mainboard mb/siemens/mc_ehl: Disable HECI #2 device 2021-11-15 11:12:22 +00:00
northbridge haswell/lynxpoint/broadwell: Use azalia_codec_init() 2021-11-11 22:44:54 +00:00
security Rename ECAM-specific MMCONF Kconfigs 2021-11-10 17:24:16 +00:00
soc soc/intel/alderlake: Disable VT-d for early silicons 2021-11-15 10:34:44 +00:00
southbridge lynxpoint/broadwell: Use azalia_codecs_init() 2021-11-11 22:45:11 +00:00
superio superio: Replace bad uses of find_resource 2021-11-04 17:36:32 +00:00
vendorcode vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 2021-11-15 09:57:35 +00:00
Kconfig Kconfig: Show console DEBUG_FUNC if OVERRIDE_LOGLEVEL is set 2021-11-13 00:20:11 +00:00