Lin Huang ecd600a0ca rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wide ... Accroding to datasheet, feedback divider register high value is only 4 bit, it currently uses 5 bit, so correct it. Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>		2017-11-28 19:14:25 +00:00
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amd	AMD platforms: Fix ASL comment that implies "\_SB" is southbridge	2017-11-28 03:53:32 +00:00
broadcom	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
dmp	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
imgtec	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
intel	intel/common/block: Add SKL CSME device ID	2017-11-28 13:10:39 +00:00
lowrisc	RISC-V boards: Stop using the config string	2017-11-07 12:31:00 +00:00
marvell	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
mediatek	soc/mediatek/mt8173: Remove cast of NULL* to void *	2017-11-03 16:03:30 +00:00
nvidia	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
qualcomm	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
rockchip	rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wide	2017-11-28 19:14:25 +00:00
samsung	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
ucb	RISC-V boards: Stop using the config string	2017-11-07 12:31:00 +00:00