Ravi Sarawadi ec7293652a soc/apollolake: Add soc core init ... Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926 Reviewed-on: https://review.coreboot.org/17168 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)		2016-11-01 17:31:59 +01:00
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broadcom/cygnus	soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK.	2016-08-31 20:23:34 +02:00
dmp/vortex86ex	src/soc: Capitalize CPU, ACPI, RAM and ROM	2016-07-31 19:27:53 +02:00
imgtec/pistachio
intel	soc/apollolake: Add soc core init	2016-11-01 17:31:59 +01:00
lowrisc/lowrisc	riscv: add the lowrisc System On Chip support	2016-10-25 22:31:06 +02:00
marvell	marvell/mvmap2315: Compose BOOTBLOCK region	2016-10-21 19:42:23 +02:00
mediatek/mt8173	src/soc: Add required space before opening parenthesis '('	2016-08-31 20:09:42 +02:00
nvidia	Makefiles: update cbfs types from bare numbers to values	2016-09-21 09:36:11 +02:00
qualcomm	soc/qualcomm/ipq40xx: Fix GPIO pull up config.	2016-10-07 17:55:19 +02:00
rdc/r8610
rockchip	rockchip/rk3399: reset system if DDR init fails	2016-10-25 17:08:58 +02:00
samsung	src/soc: Capitalize CPU, ACPI, RAM and ROM	2016-07-31 19:27:53 +02:00
ucb/riscv	soc/ucb/riscv: select BOOTBLOCK_CONSOLE	2016-08-15 18:24:42 +02:00