coreboot/src
Angel Pons ec6e03e4d8 AGESA f14/f15tn/f16kb: Deduplicate RAM settings
On AGESA f14/f15tn, various RAM-related options were defined in an enum.
However, the preprocessor mess can't compare enum values. To make AGESA
build, each board redefined them as macros, shadowing the enum elements.
Clean this up by replacing the enums with macros in AGESA headers, and
delete the now-redundant redefinitions from all the mainboards.

Note that AGESA f16kb already uses macros, but each mainboard still had
commented-out definitions. Remove them as well, as they are unnecessary.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Ie1085539013d3ae0363b1596fa48555300e45172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41666
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26 11:47:19 +00:00
..
acpi acpi/device: Add a helper function to write SoundWire _ADR 2020-05-21 08:04:12 +00:00
arch src: Remove unused 'include <string.h>' 2020-05-18 07:41:24 +00:00
commonlib src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
console treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
cpu src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
device device/pci_device: Add notion of "hidden" PCI devices 2020-05-20 09:47:35 +00:00
drivers drivers: Use SPDX identifiers 2020-05-25 22:19:21 +00:00
ec ec/lenovo/h8: Config the ec hardware ids for newer thinkpads 2020-05-26 04:41:43 +00:00
include drivers/soundwire/alc5682: Support Realtek ALC5682 SoundWire device 2020-05-22 01:48:59 +00:00
lib Remove new additions of "this file is part of" lines 2020-05-18 07:12:03 +00:00
mainboard AGESA f14/f15tn/f16kb: Deduplicate RAM settings 2020-05-26 11:47:19 +00:00
northbridge nb/intel/sandybridge: Use the new IOSAV struct API 2020-05-21 18:28:54 +00:00
security security/tpm: Use SPDX identifiers 2020-05-25 22:18:13 +00:00
soc soc/intel/jasperlake: correct IRQ routing Jasper Lake 2020-05-26 05:55:30 +00:00
southbridge src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
superio superio/winbond/w83977tf: Scope UART configuration defines more locally 2020-05-20 08:44:36 +00:00
vendorcode AGESA f14/f15tn/f16kb: Deduplicate RAM settings 2020-05-26 11:47:19 +00:00
Kconfig src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00