coreboot/src/vendorcode/intel
Sean Rhodes 47fb46e0e4 vc/intel/fsp/mtl: Update the headers to 5124_47 (13.0.228.64)
Update MTL headers from 4122_21 to 5124_47.

- PCIe EQ controls added/reworked:
  - New per-RP EQ bypass/phase controls for Gen3/4/5: Phase2, Phase3,
    Phase2–3, and overall Phase enable arrays (multiple 29-byte
    arrays)
  - New Gen3/4/5 PCET timers and TS Lock timers per-RP
  - Added PcieGen5EqPh2LocalTxOverridePreset[29]
  - Added PcieRpLtrOverrideSpecComplaint[29] (LTR override based on EP
    capability)
  - Added PcieFomsCp[29] (FOMS control policy)
  - Added PCIe configuration dump toggle (PcieCfgDump[12])
  - Added PcieClockGating[29], PciePowerGating[29], LinkDownGpios[29]
  - Added PcieFiaProgramming and PcieSetSecuredRegisterLock toggles

- Power/ASPM/LTR and platform policy:
  - Added PchDmiAspm control
  - Added ASPM Optionality Compliance test array
    (PcieRpTestAspmOc[12])
  - Added PchLanWOLFastSupport and WoWLAN DeepSx/LAN wake/Deep Sx
    policy controls
  - Added CPPM Force Alignment (CppmFaEn), PlatformAtxTelemetryUnit
  - Multiple “Reserved” fields renamed to RsvdXXX with adjusted sizes

- Thermal throttling (SoC/PCH/IOE/SATA):
  - New enable/suggested-setting toggles, customizable T0/T1/T2
    levels, and locks for SoC, PCH, IOE thermal throttling
  - SATA thermal suggested setting retained; minor reserved rename
    around it

- Storage/IO:
  - Added UfsInlineEncryption[2] enable/disable

- PMC/ADR and low-power:
  - Added comprehensive PMC ADR controls (enable, timer enable/values,
    source override/select, host reset partition) and PMC WDT enable
  - Added PmcLpmS0ixSubStateEnableMask and
    PmcPchLpmS0ixSubStateEnableMask
  - Added PchPmErDebugMode

- CPU/Power management:
  - Added CcfAutoGv, ThreeStrikeCounter, HwpLock
  - Added StepDownMode, PowerFloorManagement,
    PowerFloorDisplayDisconnect, EnableRp, PowerFloorPcieGenDowngrade
  - Added SecurityPostMemRsvd, MePostMemRsvd, various
    ReservedCpuPostMem* placeholders

- Turbo ratio controls:
  - Added TurboRatioLimitRatio[8]/NumCore[8] for P-cores and
    AtomTurboRatio* arrays for E-cores

- Graphics/Media:
  - Added ConfigureGT toggle, RC1pGtFreqEnable, RC1pMediaFreqEnable
  - Added ConfigureMedia toggle, MediaStandby
  - Added PEI logo HorizontalResolution/VerticalResolution exports

- EC hooks:
  - Added EcProvisionEav and EcBiosGuardCmdLock function pointers

- USB/Type‑C:
  - Added EnableTcssCovTypeA[4] (convert Type‑C to Type‑A option)

- Misc renames/cleanups:
  - Numerous fields renamed from generic “ReservedXX” to more explicit
    RsvdXXX arrays with adjusted sizes.

Change-Id: I76748abdf6ddcae9c7f74975e09324bb45b5f9bd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2025-09-17 12:38:24 +00:00
..
edk2 vendorcode/intel: Add edk2-stable202305 support 2024-11-06 17:00:06 +00:00
fsp vc/intel/fsp/mtl: Update the headers to 5124_47 (13.0.228.64) 2025-09-17 12:38:24 +00:00
Kconfig vendorcode/intel: Add edk2-stable202305 support 2024-11-06 17:00:06 +00:00
Makefile.mk vendorcode/intel: Add edk2-stable202305 support 2024-11-06 17:00:06 +00:00