coreboot/src/include/device
Kenji Chen 31c6e632cf PCIe: Add L1 Sub-State support.
Enable L1 Sub-State when both root port and endpoint support it.

[pg: keyed the feature to MMCONF_SUPPORT, otherwise boards
without that capability fail to build.]

Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ac04ad7e2
Original-BUG=chrome-os-partner:31424
Original-TEST=Build a image and run on Samus proto boards to check if the
settings are applied correctly. I just only have proto boards and
need someone having EVT boards to confirm the settings.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a
Original-Reviewed-on: https://chromium-review.googlesource.com/221436
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23 13:11:15 +01:00
..
dram ddr3: Plumber DIMM type to parsed structure. 2014-12-07 15:18:41 +01:00
azalia.h Correct file permissions. 2013-12-07 00:39:09 +01:00
azalia_device.h Replace includes of build.h with version.h 2014-11-20 07:28:37 +01:00
cardbus.h device/{cardbus,agp}.h: Missing header for device_t type 2014-06-25 11:32:23 +02:00
device.h devicetree: Drop dummy root_dev ops 2015-03-01 21:53:58 +01:00
drm_dp_helper.h FUI: reorganize include files 2013-07-10 02:39:42 +02:00
early_smbus.h src/include: Doxygen fixes 2015-01-09 06:04:55 +01:00
hypertransport.h Since some people disapprove of white space cleanups mixed in regular commits 2010-04-27 06:56:47 +00:00
hypertransport_def.h AMD K8 fam10: Refactor offset_unitid configuration 2015-02-20 07:04:00 +01:00
i2c.h i2c: Add software_i2c driver for I2C debugging and emulation 2014-12-30 22:07:42 +01:00
path.h sconfig: rename lapic_cluster -> cpu_cluster 2013-02-14 07:07:20 +01:00
pci.h PCIe: Add L1 Sub-State support. 2015-03-23 13:11:15 +01:00
pci_def.h PCIe: Add L1 Sub-State support. 2015-03-23 13:11:15 +01:00
pci_ehci.h x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer 2015-02-15 08:50:22 +01:00
pci_ids.h AMD Bald Eagle: Add northbridge files for new AMD processor 2015-03-10 16:43:23 +01:00
pci_ops.h pci_ops.{c,h}: Don't hide pointers behind typedefs 2014-11-05 14:45:57 +01:00
pci_rom.h RELOCATABLE_RAMSTAGE: Fix weak symbols with option ROMs 2014-12-28 19:57:16 +01:00
pciexp.h PCIe: Add L1 Sub-State support. 2015-03-23 13:11:15 +01:00
pcix.h Cosmetics and coding style fixes in devices/*. 2010-10-18 00:00:57 +00:00
pnp.h pnp: Allow setting of misc register 0xf4 in device tree 2014-09-17 17:34:16 +02:00
pnp_def.h pnp: Allow setting of misc register 0xf4 in device tree 2014-09-17 17:34:16 +02:00
resource.h x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer 2015-02-15 08:50:22 +01:00
smbus.h Cosmetics and coding style fixes in devices/*. 2010-10-18 00:00:57 +00:00
smbus_def.h - Update the device header files 2004-10-14 21:10:23 +00:00