Angel Pons ea07702f62 soc/intel/baytrail/include/soc/irq.h: Add braces ... This reduces the differences between Bay Trail and Braswell, and avoids unlikely but potential bugs regarding missing braces in macros. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ic341fe70e7d6fb4751f2fefbdedbee5c90dd8d1f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43201 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-07-25 10:23:16 +00:00
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acpi	src: Use ACPI macros	2020-07-21 18:26:47 +00:00
arch	src: Make HAVE_CF9_RESET set the FADT reset register	2020-07-20 13:23:13 +00:00
commonlib	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
console	console: Update for vboot before bootblock	2020-06-15 22:07:12 +00:00
cpu	cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include	2020-07-14 16:15:09 +00:00
device	device/pci_device.c: Do not complain about disabled devices	2020-07-24 23:12:07 +00:00
drivers	drivers/intel/gma/Kconfig: Avoid dependency hell when ignoring straps	2020-07-20 17:13:22 +00:00
ec	ec/system76_ec: add support for System76 EC	2020-07-23 09:30:22 +00:00
include	src/include/ramdetect.h: Add missing includes	2020-07-25 01:25:57 +00:00
lib	src: Remove unused 'include <types.h>'	2020-07-14 16:10:17 +00:00
mainboard	mb/intel/cedarisland: undo set trig and bufdis for NF pads	2020-07-25 10:19:18 +00:00
northbridge	nb/intel/ironlake/raminit.c: initialize 'reply.command'	2020-07-25 01:23:49 +00:00
security	security/intel/stm: Add missing <stdbool.h>	2020-07-21 20:04:12 +00:00
soc	soc/intel/baytrail/include/soc/irq.h: Add braces	2020-07-25 10:23:16 +00:00
southbridge	sb/intel/bd82x6x: Use common irqlinks.asl	2020-07-25 00:12:06 +00:00
superio	superio/common: Avoid NULL pointer dereference	2020-07-24 21:21:09 +00:00
vendorcode	vc/amd/fsp/picasso: update UPD header	2020-07-24 20:29:11 +00:00
Kconfig	arch/x86: Remove RELOCATABLE_RAMSTAGE	2020-07-06 06:17:47 +00:00