e9ce0eae74
Configure overcurrent pins for various usb ports. Configure CdClock to 3. BUG=None BRANCH=None TEST=None Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17251 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Reviewed-on: https://chromium-review.googlesource.com/408979 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
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| .. | ||
| acpi | ||
| arch | ||
| commonlib | ||
| console | ||
| cpu | ||
| device | ||
| drivers | ||
| ec | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| soc | ||
| southbridge | ||
| superio | ||
| vboot | ||
| vendorcode | ||
| Kconfig | ||