coreboot/src/northbridge
Damien Zammit d9536e34ca UPSTREAM: nb/intel/x4x: Add DMI/EP init
The values were obtained from vendor bios at runtime.
I am not 100% sure of the sequence required to initiate them,
but guessed from the gm45 code.  There may be some status bytes
needed to be polled during the sequence that is missing,
but as I don't have bios writer's datasheet it's very hard
for me to know.

Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8
Original-Signed-off-by: Damien Zammit <damien@zamaudio.com>
Original-Reviewed-on: https://review.coreboot.org/14925
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit a090ae04c2)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348405
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-01 20:36:54 -07:00
..
amd nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure 2016-05-09 20:44:11 +02:00
intel UPSTREAM: nb/intel/x4x: Add DMI/EP init 2016-06-01 20:36:54 -07:00
via kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme 2016-04-19 18:34:18 +02:00