coreboot/src/soc/intel
Maulik V Vaghela e9b1e0fe88 soc/intel/tigerlake: Update FSP stack and heap size
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB
and heap size to be minimum 128 KiB.
Updating both Kconfig to meet size requirements.
Also updated required CAR region size during boot block due to increment
in stack & heap requirement by fsp

Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20 17:57:17 +00:00
..
apollolake arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE 2019-12-19 19:31:08 +00:00
baytrail arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE 2019-12-19 19:31:08 +00:00
braswell {drivers,soc}/intel/fsp1_1: Move chipset specific logo handling to SoC 2019-12-20 17:50:28 +00:00
broadwell arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE 2019-12-19 19:31:08 +00:00
cannonlake {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC 2019-12-19 17:49:38 +00:00
common {nb,soc}: Replace min/max() with MIN/MAX() 2019-12-20 17:46:37 +00:00
denverton_ns src: Remove unused 'include <arch/cpu.h>' 2019-12-19 05:58:50 +00:00
icelake src/soc/intel: Remove unused <stdlib.h> 2019-12-19 05:41:08 +00:00
quark {nb,soc}: Replace min/max() with MIN/MAX() 2019-12-20 17:46:37 +00:00
skylake {nb,soc}: Replace min/max() with MIN/MAX() 2019-12-20 17:46:37 +00:00
tigerlake soc/intel/tigerlake: Update FSP stack and heap size 2019-12-20 17:57:17 +00:00
Kconfig soc/intel/Kconfig: Load Tiger Lake SOC Kconfig 2019-12-11 11:37:45 +00:00