John Zhao baf54ec272 mb/google/brya: Add EC_HOST_EVENT_USB_MUX ... This changes adds the EC_HOST_EVENT_USB_MUX to be dark resume source. BUG=None TEST=Build coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I6f4dcbc60a6cb131f28de205bd9ef436f2b508eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55126 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-06-07 16:46:07 +00:00
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acpi	acpi/device: Add ability to generate proper _STA for PowerResource	2021-06-07 05:21:30 +00:00
arch	arch/x86/acpi_bert_storage: change return type of bert_errors_present	2021-05-30 20:16:12 +00:00
commonlib	src/intel/xeon_sp: add hardware error support (HEST)	2021-06-04 12:38:32 +00:00
console
cpu	cpu/intel/model_206ax/acpi.c: Do not report P_BLK	2021-06-07 11:36:53 +00:00
device	device: Consider fw_config probing in is_dev_enabled()	2021-05-24 16:55:39 +00:00
drivers	drivers/pcie/rtd3/device: Add PCIe RTD3 driver	2021-06-07 11:35:47 +00:00
ec	ec: Add Star Labs ITE 8987E support	2021-06-04 17:20:56 +00:00
include	acpi/device: Add ability to generate proper _STA for PowerResource	2021-06-07 05:21:30 +00:00
lib	drivers/pc80/mc146818rtc: Check date and time for sanity	2021-05-30 20:28:14 +00:00
mainboard	mb/google/brya: Add EC_HOST_EVENT_USB_MUX	2021-06-07 16:46:07 +00:00
northbridge	nb/intel/x4x/rcven.c: Guard macro parameters	2021-05-28 10:05:37 +00:00
security	3rdparty/intel-sec-tools: Update to support Boot Guard	2021-06-07 11:36:22 +00:00
soc	soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB	2021-06-07 16:04:36 +00:00
southbridge	sb/intel/lynxpoint: Drop P_LVLx support in FADT	2021-06-07 11:37:25 +00:00
superio
vendorcode	soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB	2021-06-07 16:04:36 +00:00
Kconfig	option: Allow mainboards to implement the API	2021-05-28 11:37:25 +00:00