coreboot/src
Xiang Wang e8d0c0092a riscv: delete src/arch/riscv/prologue.inc
This code was copied from x86. It is not needed for RISC-V.

Change-Id: If6c3bfdc4090e45d171e68a28d27c38dabe91687
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27544
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 19:02:13 +00:00
..
acpi
arch riscv: delete src/arch/riscv/prologue.inc 2018-07-30 19:02:13 +00:00
commonlib security/tpm: Use unique CBMEM names for TCPA logs 2018-07-30 15:47:23 +00:00
console arch/x86: Drop leftover ROMCC console support 2018-06-08 03:31:12 +00:00
cpu cpu/intel/microcode: Add helper functions to get microcode info 2018-07-30 18:49:47 +00:00
device pnp_device: don't treat missing PNP_MSC devicetree entry as error 2018-07-29 15:06:41 +00:00
drivers drivers/i2c/da7219: Allow disabling micbias-pulse feature 2018-07-30 18:45:44 +00:00
ec ec/lenovo/h8/acpi: Fix ACPI error in _INI 2018-07-30 18:59:51 +00:00
include cpu/intel/microcode: Add helper functions to get microcode info 2018-07-30 18:49:47 +00:00
lib util/cbmem: Add cbmem TCPA log support 2018-07-28 16:58:30 +00:00
mainboard mb/google/stout: Use new PMBASE API 2018-07-30 18:59:20 +00:00
northbridge northbridge/nehalem: add MCHBAR AND/OR/AND_OR macros 2018-07-30 12:33:36 +00:00
security security/vboot: Enable TCPA log extension 2018-07-30 15:46:11 +00:00
soc soc/amd/stoneyridge/northbridge.c: Create a way to change eDP training value 2018-07-30 18:57:06 +00:00
southbridge sb/intel/bd82x6x/finalize: Use new PMBASE API 2018-07-30 18:58:22 +00:00
superio sio/smsc/fdc37n972: add missing pnp_conf_mode field to ops struct 2018-07-26 14:22:28 +00:00
vendorcode vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.5 2018-07-25 18:38:39 +00:00
Kconfig Kconfig: Make the EM100 config option common 2018-07-16 07:41:14 +00:00