Sean Rhodes e8b6b07bfc intel/tigerlake: Add missing IRQ for CNVi ... Add CNVi (14.3) to IRQ Table to stop dmesg error: iwlwifi 0000:00:14.3: can't derive routing for PCI INT F iwlwifi 0000:00:14.3: PCI INT F: not connected Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5b793997f9ea954217871eb4656dacf6abe77e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-10-18 12:33:17 +00:00
..
alderlake	soc/intel: transition full control over PM Timer from FSP to coreboot	2021-10-17 13:59:04 +00:00
apollolake	soc/intel/{common,apl,glk}: guard PM Timer option on SoCs w/o PM Timer	2021-10-17 14:00:10 +00:00
baytrail	soc/intel: drop P_BLK support	2021-10-13 18:05:05 +00:00
braswell	soc/intel: drop P_BLK support	2021-10-13 18:05:05 +00:00
broadwell	soc/intel/broadwell/pcie.c: Simplify AND-mask	2021-10-15 00:00:13 +00:00
cannonlake	soc/intel: transition full control over PM Timer from FSP to coreboot	2021-10-17 13:59:04 +00:00
common	soc/intel/{common,apl,glk}: guard PM Timer option on SoCs w/o PM Timer	2021-10-17 14:00:10 +00:00
denverton_ns	soc/intel/{skl,cnl,dnv}: disable PM ACPI timer if chosen	2021-10-17 13:58:15 +00:00
elkhartlake	soc/intel: transition full control over PM Timer from FSP to coreboot	2021-10-17 13:59:04 +00:00
icelake	soc/intel: transition full control over PM Timer from FSP to coreboot	2021-10-17 13:59:04 +00:00
jasperlake	soc/intel: transition full control over PM Timer from FSP to coreboot	2021-10-17 13:59:04 +00:00
quark	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
skylake	soc/skylake: Make VT-d controllable from CMOS option	2021-10-18 12:32:43 +00:00
tigerlake	intel/tigerlake: Add missing IRQ for CNVi	2021-10-18 12:33:17 +00:00
xeon_sp	soc/intel: drop P_BLK support	2021-10-13 18:05:05 +00:00
Kconfig	fsp2_0: Gather Kconfig declarations	2020-04-05 23:26:24 +00:00