Philipp Hug 7524400242 uart/sifive: make divisor configurable ... The SiFive UART on the HiFive Unleashed uses the tlclk as input clock which runs at coreclk / 2. The input frequency is configured in the board code depending on the current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz) Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>		2018-09-13 15:32:53 +00:00
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Kconfig
Makefile.inc
oxpcie.c
oxpcie_early.c
pl011.c
pl011.h
sifive.c	uart/sifive: make divisor configurable	2018-09-13 15:32:53 +00:00
uart8250io.c	arch/x86: Drop leftover ROMCC console support	2018-06-08 03:31:12 +00:00
uart8250mem.c
uart8250reg.h
util.c