coreboot/src/arch
David Hendricks e85f4eb1b0 armv7: update sync barrier usage in dcache_op_set_way()
This moves the dsb() before the loop to sync any outstanding memory
accesses, and adds an isb() after the loop to ensure all outstanding
instructions are completed.

Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2929
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29 21:12:54 +01:00
..
armv7 armv7: update sync barrier usage in dcache_op_set_way() 2013-03-29 21:12:54 +01:00
x86 x86: dynamic cbmem: fix acpi reservations 2013-03-26 18:06:11 +01:00