Carl-Daniel Hailfinger e855c968c1 arch/x86/pci_ops_conf1.c is already linked into stage1 and SHARED. ... Don't link it into initram as well. With this change, I can compile stage0, stage1, initram and large parts of stage2 without problems for the M57SLI target. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@770 f3766cd6-281f-0410-b1cd-43a5c92072e9		2008-08-15 19:56:41 +00:00
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adl	Convert stage2 and initram makefile rules from object to source files.	2008-08-02 20:56:11 +00:00
amd	Convert stage2 and initram makefile rules from object to source files.	2008-08-02 20:56:11 +00:00
artecgroup	artecgroup/dbe62: Fix SPD_NUM_COLUMNS value (DIMM page size)	2008-08-13 17:21:09 +00:00
emulation	CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE was never used. Kill	2008-08-15 16:41:37 +00:00
gigabyte	arch/x86/pci_ops_conf1.c is already linked into stage1 and SHARED.	2008-08-15 19:56:41 +00:00
pcengines	CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE was never used. Kill	2008-08-15 16:41:37 +00:00
Kconfig	The m57sli almost builds. It's pretty empty. The dtc is not run .	2008-08-01 17:03:22 +00:00