e7e9b874e1
RAM_ID0 was used as the table MSB, and RAM_ID2 as the LSB. This is the opposite of expected. Reverse these two GPIOS to make current boards work. For future boards, we will change the signal names on the schematic to be consistent. TEST=Manual. Build image, verify Hynix board loads correct SPD. BUG=chrome-os-partner:19636. BRANCH=None. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I044e7ee696f19fe6fd5911e17317190832f675c5 Reviewed-on: https://gerrit.chromium.org/gerrit/60162 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Dave Parker <dparker@chromium.org> Commit-Queue: Dave Parker <dparker@chromium.org> |
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| .. | ||
| arch | ||
| console | ||
| cpu | ||
| device | ||
| drivers | ||
| ec | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| southbridge | ||
| superio | ||
| vendorcode | ||
| Kconfig | ||