coreboot/src/northbridge
Ricardo Ribalda Delgado a132892de6 amd/pi: Make BottomIo position configurable
Some PCI peripherals, such as FPGA accelerators, require a great amount
of memory mapped IO. This patch allows the user to select at build time
the bottom IO to leave enough space for such devices.

We cannot calculate this value at runtime because it has to be set
before the PCI devices are enumerated.

Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d
Credit-to: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/17980
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-01-09 18:13:48 +01:00
..
amd amd/pi: Make BottomIo position configurable 2017-01-09 18:13:48 +01:00
intel nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h> 2017-01-06 18:15:03 +01:00
via buildsystem: Drop explicit (k)config.h includes 2016-12-08 19:46:53 +01:00