coreboot/src
Duncan Laurie e68042f021 soc/intel/cannonlake: Add DPTF ACPI code
Define the constants that DPTF expects from the SOC in order to
use the common DPTF ACPI code.  For cannonlake this indicates
the CPU device is called B0D4 and is at PCI address 00:04.0.

Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29759
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04 10:20:23 +00:00
..
acpi
arch arch/power8: Rename to ppc64 2018-11-30 20:02:17 +00:00
commonlib src: Remove duplicated round up function 2018-11-29 12:17:45 +00:00
console (console,drivers/uart)/Kconfig: Fix dependencies 2018-11-21 22:49:48 +00:00
cpu cpu/intel/fsp_model_406dx: Drop dead microcode reference 2018-12-03 13:40:46 +00:00
device arch/power8: Rename to ppc64 2018-11-30 20:02:17 +00:00
drivers drivers/intel/fsp1_1/romstage.c: Fix typo 2018-12-04 10:14:33 +00:00
ec ec/google/wilco: Fix extended event handling 2018-12-04 10:18:16 +00:00
include include/device/smbus.h: Don't use device_t 2018-12-03 13:01:15 +00:00
lib src: Remove duplicated round up function 2018-11-29 12:17:45 +00:00
mainboard mb/google/sarien: Enable WWAN detection 2018-12-04 10:15:52 +00:00
northbridge nb/intel/gm45: Make fetching the blc_pwm freq global 2018-12-03 13:03:13 +00:00
security tss: implement tlcl_save_state 2018-11-28 18:32:59 +00:00
soc soc/intel/cannonlake: Add DPTF ACPI code 2018-12-04 10:20:23 +00:00
southbridge sb/intel/i82801jx: Fix the x_pm2_cnt_blk addrl 2018-12-03 13:27:37 +00:00
superio src: Add required space after "switch" 2018-11-19 08:17:06 +00:00
vendorcode vendorcode/cavium: Supply bdk_pop and bdk_dpop definitions 2018-11-28 11:47:59 +00:00
Kconfig cpu/x86/Kconfig.debug: Move more options here 2018-11-23 08:38:31 +00:00