erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
coreboot/src
History
Tim Chu e41f595310 arch/x86/smbios: Update memory_array_handle for SMBIOS type 19 
Update memory array handle for SMBIOS type 19.

TEST=Execute "dmidecode -t 19" to check if memory array handle is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I49078b870bac3c6162913b91651ec09632800f1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16 11:03:37 +00:00
..
acpi acpigen: Add more useful helper functions 2020-11-09 07:30:01 +00:00
arch arch/x86/smbios: Update memory_array_handle for SMBIOS type 19 2020-11-16 11:03:37 +00:00
commonlib commonlib: Add timestamp values for forced delays 2020-11-16 11:01:37 +00:00
console console: Override uart base address 2020-11-09 07:46:10 +00:00
cpu cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers 2020-11-10 06:18:05 +00:00
device device: Move pci_dev_is_wake_source function 2020-11-09 07:37:57 +00:00
drivers drivers/i2c/dw: Check for TX_ABORT in transfer 2020-11-16 11:00:57 +00:00
ec ec/purism/librem/ec.asl: End comment 2020-11-09 07:28:53 +00:00
include src: Change bare 'unsigned' to 'unsigned int' 2020-11-16 11:03:16 +00:00
lib lib/libpayload: Replace strapping_ids with new board configuration entry 2020-10-30 15:25:28 +00:00
mainboard mb/google/zork: Init fingerprint GPIOs for boot vs resume 2020-11-16 11:03:25 +00:00
northbridge mrc_cache: Move code for triggering memory training into mrc_cache 2020-11-13 22:57:50 +00:00
security sec/intel/cbnt: Stitch in ACMs in the coreboot image 2020-11-10 06:17:24 +00:00
soc src: Change bare 'unsigned' to 'unsigned int' 2020-11-16 11:03:16 +00:00
southbridge sb/intel/lynxpoint/acpi/pch.asl: Drop unused FD definitions 2020-11-13 13:05:05 +00:00
superio superio/nuvoton: Factor out equivalent Kconfig option 2020-10-19 07:06:20 +00:00
vendorcode vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatch 2020-11-16 11:03:00 +00:00
Kconfig soc/intel/xeon_sp: Move function debug macros 2020-10-29 16:44:19 +00:00