aa8d7721d4
From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SPD_BIN_H
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#define SPD_BIN_H
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#include <arch/early_variables.h>
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#include <stdint.h>
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#include <commonlib/region.h>
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#define SPD_PAGE_LEN 256
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#define SPD_PAGE_LEN_DDR4 512
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#define SPD_PAGE_0 (0x6C >> 1)
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#define SPD_PAGE_1 (0x6E >> 1)
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0B
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#define SPD_DRAM_LPDDR3_INTEL 0xF1
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#define SPD_DRAM_LPDDR3_JEDEC 0x0F
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#define SPD_DRAM_DDR4 0x0C
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define DDR3_ORGANIZATION 7
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#define DDR3_BUS_DEV_WIDTH 8
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#define DDR4_ORGANIZATION 12
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#define DDR4_BUS_DEV_WIDTH 13
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#define DDR3_SPD_PART_OFF 128
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#define DDR3_SPD_PART_LEN 18
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#define LPDDR3_SPD_PART_OFF 128
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#define LPDDR3_SPD_PART_LEN 18
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#define DDR4_SPD_PART_OFF 329
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#define DDR4_SPD_PART_LEN 20
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#define LPDDR4_SPD_PART_OFF 329
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#define LPDDR4_SPD_PART_LEN 20
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struct spd_block {
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u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */
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u8 *spd_array[CONFIG_DIMM_MAX];
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/* Length of each dimm */
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u16 len;
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};
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void print_spd_info(uint8_t spd[]);
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/* Return 0 on success & -1 on failure */
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int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index);
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void dump_spd_info(struct spd_block *blk);
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void get_spd_smbus(struct spd_block *blk);
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/* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and
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verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */
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int read_ddr3_spd_from_cbfs(u8 *buf, int idx);
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#endif
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