coreboot/src/soc
Gang Chen cae81a5674 soc/intel/xeon_sp/gnr: Support fast boot
Fast boot will used pre-saved hardware configuration data to
accelerate the boot process, e.g. DDR training is skipped by using
pre-saved training data. Enable fast boot on cold and warm resets
by default.

Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-03 12:09:06 +00:00
..
amd soc/amd/cezanne: Add AMD Renoir SOC support 2024-06-18 13:08:00 +00:00
cavium tree: Use <stdio.h> for snprintf 2024-05-29 10:33:54 +00:00
example/min86
ibm/power9 soc/ibm/power9/*: add file structure for SOC 2024-05-02 23:14:22 +00:00
intel soc/intel/xeon_sp/gnr: Support fast boot 2024-07-03 12:09:06 +00:00
mediatek soc/mediatek/mt8188: Respect ARM64_BL31_OPTEE_WITH_SMC option 2024-06-21 01:49:49 +00:00
nvidia soc/nvidia: Remove unneeded white spaces 2024-07-01 13:38:20 +00:00
qualcomm tree: Use <console/console.h> only when used 2024-07-03 04:39:42 +00:00
rockchip tree: Remove duplicated <soc/gpio.h> 2024-05-30 14:40:32 +00:00
samsung tree: Remove blank lines before '}' and after '{' 2024-04-11 19:19:08 +00:00
sifive soc/sifive/fu540/chip.c: Add RAM resources 2024-06-12 19:16:26 +00:00
ti
ucb/riscv