Read-only mirror of https://review.coreboot.org/coreboot.git. Synced every hour. We don't handle Pull Requests.
https://coreboot.org
- C 93.8%
- ASL 2.2%
- Makefile 1.1%
- C++ 0.5%
- Pawn 0.5%
- Other 1.8%
e2cf7abe0a
On x86 there is a 16-byte alignment requirement for the addresses containing the CPU microcode. The cbfs files containing the microcode are used in memory-mapped fashion when loading new mircocode. Therefore, the data payload's address/offset of a cbfs file in flash dictates the resulting alignment. Fix this by processing the CPU microcode cbfs file separately as it uses $(CBFSTOOL) to find the proper location within the provided rom image. BUG=chrome-os-partner:20100 BRANCH=None TEST=Manually inspected cbfs layout: CBFS @ Offset 0x00700000 into 0x00800000 ROM size [0xfff00000] cmos_layout.bin type cmos layout (0x1aa) @ 0xfff00028, 0x48c (1164) bytes [0xfff004c0] pci8086,0406.rom type optionrom (0x30) @ 0xfff004f8, 0x10000 (65536) bytes [0xfff10500] cpu_microcode_blob.bin type microcode (0x53) @ 0xfff10560, 0x9c40 (40000) bytes [0xfff1a1c0] config type raw (0x50) @ 0xfff1a1e8, 0x157f (5503) bytes [0xfff1b780] fallback/vboot type stage (0x10) @ 0xfff1b7a8, 0x3ad3 (15059) bytes [0xfff1f280] (empty) type null (0xffffffff) @ 0xfff1f2a8, 0xcd8 (3288) bytes [0xfff1ff80] fallback/romstage type stage (0x10) @ 0xfff1ffe4, 0xa001 (40961) bytes [0xfff2a000] fallback/coreboot_ram type stage (0x10) @ 0xfff2a038, 0x15373 (86899) bytes [0xfff3f3c0] fallback/payload type payload (0x20) @ 0xfff3f3f8, 0xd00e (53262) bytes [0xfff4c440] u-boot.dtb type unknown (0xac) @ 0xfff4c468, 0x1e4b (7755) bytes [0xfff4e2c0] (empty) type null (0xffffffff) @ 0xfff4e2e8, 0x51cd8 (335064) bytes [0xfff9ffc0] mrc.bin type mrc (0xab) @ 0xfffa0000, 0x2d8b8 (186552) bytes [0xfffcd8c0] (empty) type null (0xffffffff) @ 0xfffcd8e8, 0x1e6d8 (124632) bytes [0xfffebfc0] spd.bin type mrc (0xab) @ 0xfffec000, 0x200 (512) bytes [0xfffec200] (empty) type null (0xffffffff) @ 0xfffec228, 0x13418 (78872) bytes Change-Id: Icc676a1c76c368d77e48cf573c6f846301da42a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58238 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> |
||
|---|---|---|
| 3rdparty@ba8caa30bd | ||
| configs | ||
| documentation | ||
| payloads | ||
| src | ||
| util | ||
| .gitignore | ||
| COPYING | ||
| Makefile | ||
| Makefile.inc | ||
| PRESUBMIT.cfg | ||
| README | ||
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.