Robert Zieba e2bde83a51 soc/amd/cezanne: Turn off gpp clock request for disabled devices ... The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-03-23 19:37:36 +00:00
..
cezanne	soc/amd/cezanne: Turn off gpp clock request for disabled devices	2022-03-23 19:37:36 +00:00
common	soc/amd/common/psp_verstage: Write postcodes after ESPI init	2022-03-23 16:13:42 +00:00
picasso	soc/amd/picasso: Add counter initializers	2022-03-17 17:39:08 +00:00
sabrina	soc/amd/sabrina: Add counter initializers	2022-03-17 17:38:54 +00:00
stoneyridge	soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER	2022-03-09 19:01:15 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00