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coreboot/src/include/cpu/intel
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Kyösti Mälkki e1e658ad29 UPSTREAM: intel: Fix romstage main() with asmlinkage 
Backport from haswell.

Change-Id: I585639f8af47bd1d8c606789ca026c6d2d0cc785
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15225
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit e325b223a2)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354188
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-21 17:13:34 -07:00
..
hyperthreading.h Intel CPUs: execute microcode update only once per core 2012-07-02 15:49:07 +02:00
l2_cache.h tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
microcode.h cpu/intel/microcode: allow microcode to be loaded in romstage 2016-02-10 18:08:28 +01:00
romstage.h UPSTREAM: intel: Fix romstage main() with asmlinkage 2016-06-21 17:13:34 -07:00
speedstep.h tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
turbo.h tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00