coreboot/src/arch
Marshall Dawson 1d8d369dad x86/acpi: Add BERT table
Create a structure for the Boot Error Record Table, and a generic
table generator function.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 14:50:34 +00:00
..
arm src/arch: Fix typo 2018-08-09 15:56:02 +00:00
arm64 arm64: Factor out common parts of romstage execution flow 2018-08-17 21:29:46 +00:00
mips arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm) 2018-08-07 20:55:58 +00:00
power8 arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm) 2018-08-07 20:55:58 +00:00
riscv riscv: add entry assembly file for RAMSTAGE 2018-09-05 10:04:57 +00:00
x86 x86/acpi: Add BERT table 2018-09-07 14:50:34 +00:00